3. Without getting too technical, the new A-series APUs are made using a 32nm manufacturing process and each processor core on the "CPU side" of the APU has 1mb of its own Level 2 cache.
4. Friday's glitch started with an errant heater in one of the three auxiliary power units (APUs) in Endeavour - all of which must be in perfect working order for a launch to be allowed to proceed.
5. Friday's glitch started with an errant heater in one of the three auxiliary power units (APUs) in Endeavour - all of which must be in perfect working order for a launch to be allowed to proceed.